ort82g5 Lattice Semiconductor Corp., ort82g5 Datasheet - Page 83

• Manufacturer Part Number: ort82g5
• Description: Xaui And Fc Fpscs
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
This section describes device I/O signals to/from the embedded core.
Table 41. FPSC Function Pin Descriptions
Common Signals for Both SERDES Quad A and B
PASB_RESETN
PASB_TRISTN
PASB_PDN
PASB_TESTCLK
PBIST_TEST_ENN
PLOOP_TEST_ENN
PMP_TESTCLK
PMP_TESTCLK_ENN
PSYS_DOBISTN
PSYS_RSSIG_ALL
SERDES Quad A and B Pins
REFCLKN_A
REFCLKP_A
REFCLKN_B
REFCLKP_B
REXT_A
REXT_B
REXTN_A
REXTN_B
HDINN_AA (ORT82G5 only)
HDINP_AA (ORT82G5 only)
HDINN_AB (ORT82G5 only)
HDINP_AB (ORT82G5 only)
HDINN_AC
HDINP_AC
HDINN_AD
HDINP_AD
HDINN_BA (ORT82G5 only)
HDINP_BA (ORT82G5 only)
HDINN_BB (ORT82G5 only)
HDINP_BB (ORT82G5 only)
HDINN_BC
HDINP_BC
HDINN_BD
HDINP_BD
SERDES quad A and B Pins
HDOUTN_AA (ORT82G5 only)
HDOUTP_AA (ORT82G5 only)
HDOUTN_AB (ORT82G5 only)
Symbol
I/O
—
—
—
—
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Active low reset for the embedded core. All non-SERDES specific registers
(addresses 308***, 309***, 30A***) in the embedded core are not reset.
Active low 3-state for embedded core output buffers.
Active low power down of all SERDES blocks and associated I/Os.
Clock input for BIST and loopback test.
Selection of PASB_TESTCLK input for BIST test.
Selection of PASB_TESTCLK input for loopback test.
Clock input for microprocessor in test mode.
Selection of PMP_TESTCLK in test mode.
Input to start BIST test.
Output result of BIST test.
CML reference clock input—SERDES quad A.
CML reference clock input—SERDES quad A.
CML reference clock input—SERDES quad B.
CML reference clock input—SERDES quad B.
Reference resistor – SERDES quad A.
Reference resistor – SERDES quad B.
Reference resistor – SERDES quad -. A 3.32 K W ± 1% resistor must be connected
across REXT_B and REXTN_B. This resistor should handle a current of 300 µA.
Reference resistor – SERDES quad B. A 3.32 K Ω ± 1% resistor must be con-
nected across REXT_B and REXTN_B. This register should handle a current of
300 µA
High-speed CML receive data input – SERDES quad A, channel A.
High-speed CML receive data input – SERDES quad A, channel A.
High-speed CML receive data input – SERDES quad A, channel B.
High-speed CML receive data input – SERDES quad A, channel B.
High-speed CML receive data input – SERDES quad A, channel C.
High-speed CML receive data input – SERDES quad A, channel C.
High-speed CML receive data input – SERDES quad A, channel D.
High-speed CML receive data input – SERDES quad A, channel D.
High-speed CML receive data input – SERDES quad B, channel A.
High-speed CML receive data input – SERDES quad B, channel A.
High-speed CML receive data input – SERDES quad B, channel B.
High-speed CML receive data input – SERDES quad B, channel B.
High-speed CML receive data input – SERDES quad B, channel C.
High-speed CML receive data input – SERDES quad B, channel C.
High-speed CML receive data input – SERDES quad B, channel D.
High-speed CML receive data input – SERDES quad B, channel D.
High-speed CML transmit data output – SERDES quad A, channel A.
High-speed CML transmit data output – SERDES quad A, channel A.
High-speed CML transmit data output – SERDES quad A, channel B.
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ORCA ORT42G5 and ORT82G5 Data Sheet
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