ort82g5 Lattice Semiconductor Corp., ort82g5 Datasheet - Page 60

• Manufacturer Part Number: ort82g5
• Description: Xaui And Fc Fpscs
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
which follows the Power PC convention where address bit 0 is the MSb and address bit 31 is the LSb. The MPI
maps bits MPI_ADDR[14:31] to bits [17:0] of the system address bus. The User Master Interface (UMI) has an 18-
bit address bus and uses the opposite notation, where address line 17 is the MSb and address line 0 is the LSb.
The UMI maps bits um_addr[17:0] to bits [17:0] of the system address bus. Because of the address mapping done
by the MPI and UMI, the same hexadecimal address value is valid for both interfaces.
The UMI, internal and microprocessor interface data buses have both 32-bit data and 4-bit parity fields and the
data fields are mapped 1:1 to each other, i.e., bit 0 is bit 0 for all three buses. The bit ordering is specific to the tar-
geted functional block. In the memory map, only bits [0:7] are specified and the convention followed for sub-field
descriptions is to map the bits in the description directly to the bit order given in the bit column. For example, to
select channel C as the source for the transmit and receive clocks, the register at location 30A00 should have bits
0, 2, 4 and 6 set to zero and bits 1, 3, 5 and 7 set to one.
In the example in the previous paragraph, the bits being set are control bits and are independent of the MSb/LSb
convention used. The resulting bit pattern 01010101 maps to the hexadecimal value AA if the left-most bit is con-
sidered the LSb and to 55 if the right-most bit is considered the LSb. In some cases, however, the data represents
the value of a specific parameter, such as a size or threshold level, and the value may be stored at more than one
address location, since each location can hold only 8 bits of data. For a given register, either the MSb or the LSb bit
position is specified explicitly in the memory map. If the parameter value extends over multiple register locations,
the relative bit or byte ordering is also specified. For additional information on the MPI and the system bus, see
Technical Note TN1017, ORCA Series 4 MPI/System Bus.
Table 28. ORT42G5 Memory Map
SERDES Alarm Registers (Read Only, Clear on Read), xx = [AC, AD, BC or BD]
30020 - AC
30030 - AD
30120 - BC
30130 - BD
SERDES Alarm Mask Registers (Read/Write), xx = [AC, AD, BC or BD]
30021 - AC
30031 - AD
30121 - BC
30131 - BD
Absolute
Address
(0x)
[4:7] Not used
Bit
[0]
[1]
[2]
[3]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Reserved
LKI_xx
Not used
Not used
Reserved
MLKI_xx
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Name
Reset
Value
(0x)
FF
00
Reserved
Receive PLL Lock Indication, Channel xx. LKI_xx = 1 indicates the
receive PLL is locked.
Reserved
Reserved
Not used
Reserved, must be set to 1. Set to 1 on device reset.
Mask Receive PLL Lock Indication, Channel xx.
Reserved. Must be set to 1. Set to 1 on device reset.
Reserved. Must be set to 1. Set to 1 on device reset.
Reserved. Must be set to 1. Set to 1 on device reset.
Reserved. Must be set to 1. Set to 1 on device reset.
Reserved. Must be set to 1. Set to 1 on device reset.
Reserved. Must be set to 1. Set to 1 on device reset.
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ORCA ORT42G5 and ORT82G5 Data Sheet
Description