ort82g5 Lattice Semiconductor Corp., ort82g5 Datasheet - Page 56

• Manufacturer Part Number: ort82g5
• Description: Xaui And Fc Fpscs
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Table 24. Decoding of SCHAR_CHAN
The receive characterization test mode is entered when SCHAR_ENA=1 and SCHAR_TXSEL=0, In this mode,
one of the channels of SERDES outputs is observed at chip ports as shown in Table 25. The channel that is
observed is also based on the decoding of SCHAR_CHAN as shown in Table 25.
Table 25. SERDES Receive Characterization Mode
Embedded Core Block RAM
There are two independent memory blocks (labeled A and B) built-into the Embedded ASIC Core (EAC). Each
memory block has a capacity of 4K words by 36 bits. These two memory blocks (also called “slices”) are in addition
to the block RAMs found in the FPGA portion of the ORT82G5.
Although the memory blocks/slices are in the EAC part of the chip, they do not interact with the rest of the EAC cir-
cuits, but are standalone memories designed specifically to increase RAM capacity in the ORT82G5 chip. They can
be used by logic implemented in the FPGA portion of the FPSC. Figure 34 represents one of the two available
memory slices built into the EAC. The index “x” refers to the memory slice (x=A for slice A, x=B for slice B). Each
memory slice is organized into two sections, which are also labeled as A and B. In Figure 34, SDRAM A is one sec-
tion of slice x, and SDRAM B is another section of slice x. Data can be written to both sections of a slice indepen-
dently. However, a read access can access only one of sections A or B at any given time (CSR_x=0 selects section
A, CSR_x=1 selects section B).
The 36 bits written to or read from the memory slice are composed of 32 bits of data (bits 31:24, 23:16, 15:8, 7:0),
and 4 bits of parity (bits 35,34,33,32). The core performs no parity checking functions. The data read from the
memory is registered so that it works as a pipelined synchronous memory block.
For illustration purposes, assuming that the memory slice in Figure 34 is slice A (x=A), then certain signals apply to
both sections of slice A. These include D_A[35:0], CKW_A, AW_A[10:0], BYTEWN_A[3:0], Q_A[35:0], CKR_A,
CSR_A, and AR_A[10:0]. The BYTEWN_A[3:0] are byte and parity write enable bits for each byte and parity bit of
data being written.
BYTEWN_A[3] is associated with D_A[35,31:24].
BYTEWN_A[2] is associated with D_A[34,23:16].
BYTEWN_A[1] is associated with D_A[33,15:8].
BYTEWN_A[0] is associated with D_A[32,7:0].
The signals that are unique to each section of slice A are:
CSWA_A --enables writing to section A of slice A
CSWB_A -- enables writing to section B of slice A
SCHAR_CHAN0
0
1
0
1
SERDES Output
LDOUTBx[9:0]
BYTSYNCBx
WDSYNCBx
RBC0Bx
RBC1Bx
CVOBx
SCHAR_CHAN1
56
0
0
1
1
ORCA ORT42G5 and ORT82G5 Data Sheet
PSCHAR_BYTSYNC
PSCHAR_WDSYNC
PSCHAR_LDIO[9:0]
PSCHAR_CKIO0
PSCHAR_CKIO1
PSCHAR_CV
Chip Port
Channel
BA
BB
BC
BD