ort82g5 Lattice Semiconductor Corp., ort82g5 Datasheet - Page 4

• Manufacturer Part Number: ort82g5
• Description: Xaui And Fc Fpscs
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Embedded Function Features
• High-speed SERDES with programmable serial data rates over the range 0.6 to 3.7 Gbps. Operation has been
• Asynchronous operation per receive channel with the receiver frequency tolerance based on one reference clock
• Ability to select full-rate or half-rate operation per transmit or receive channel by setting the appropriate control
• Programmable one-half amplitude transmit mode for reduced power in chip-to-chip application.
• Transmit preemphasis (programmable) for improved receive data eye opening.
• 32-bit (8b/10b) or 40-bit (raw data) parallel internal bus for data processing in FPGA logic.
• Provides a 10 Gbps backplane interface to switch fabric. Also supports multiple port cards at 2.5 Gbps.
• 3.125 Gbps SERDES compliant with XAUI serial data specification for 10 G Ethernet applications with protec-
• IEEE 802.3ae compliant XAUI transceiver. Includes embedded IEEE 802.3ae-based XAUI link state machine.
• Compliant to FC-0 specification for 1 Gbps, 2Gbps, 10 Gbps (FC-XAUI) modes. Includes Fibre Channel link state
• High-Speed Interface (HSI) function for clock/data recovery serial backplane data transfer without external
• SERDES has low-power CML buffers. Support for 1.5V/1.8V I/Os. Allows use with optical transceiver, coaxial
• Power down option of SERDES HSI receiver or transmitter on a per-channel basis.
• Automatic lock to reference clock in the absence of valid receive data.
• High-speed and low-speed loopback test modes.
• Requires no external component for clock recovery and frequency synthesis.
• SERDES characterization pins available to control/monitor the internal interface to one SERDES block
• SERDES HSI automatically recovers from loss-of-clock once its reference clock returns to normal operating
• Built-in boundary scan (IEEE
• FIFOs can align incoming data either across all eight channels (ORT82G5 only), across one or two groups of
• Addition of two 4K x 36 dual-port RAMs with access to the programmable logic.
• The ORT82G5 is pinout compatible to the ORCA ORSO82G5 SONET backplane driver FPSC. The ORT42G5 is
demonstrated on design tolerance devices at 3.7 Gbps across 26 in. of FR-4 backplane and at 3.125 Gbps
across 40 in. of FR-4 backplane across temperature and voltage specifications.
per block channels (separate PLL per channel).
registers.
tion.
machine.
clocks.
copper media, shielded twisted pair wiring or high-speed backplanes such as FR-4.
(ORT82G5 only).
state.
interface.
four channels, or across two or four groups of two channels. Alignment is done either using comma characters or
by using the /A/ character in XAUI mode. Optionally, the alignment FIFOs can be bypassed for asynchronous
operation between channels. (Each channel includes its own clock and frame pulse or comma detect.)
pin compatible to the ORSO42G5.
®
1149.1 and 1149.2 JTAG) for the programmable I/Os, not including the SERDES
4
ORCA ORT42G5 and ORT82G5 Data Sheet