ort82g5 Lattice Semiconductor Corp., ort82g5 Datasheet - Page 36

• Manufacturer Part Number: ort82g5
• Description: Xaui And Fc Fpscs
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
For the ORT82G5, the SYNC2_[A1,A2,B1,B2]_OOS, SYNC4_[A:B]_OOS,and SYNC8_OOS signals can be used
with CH248_SYNC_xx to determine if the desired multi-channel alignment was successful. If, when
CH248_SYNC_xx goes high the corresponding OOS signal remains low, the data being transferred across the
core/FPGA interface is correctly aligned between channels. Note that only the signals corresponding to the
selected alignment mode will be meaningful.
For both devices, the code violation signals will only be valid if the corresponding CV_SELxx = 1. (If 8b10bR=0,
CV_SEL should also be zero. The CV_xx_OR signals are obtained by ORing four code violation signals from the
1:4 DEMUX block. These are primarily indicators of received signal quality since a single code violation will not
force a loss of sync (LOS) state in the word alignment state machines. Since these signals come from the DEMUX
block, if multi-channel alignment is enabled, the code violation signals correspond to data that must still be multi-
channel aligned. Hence these signals provide advance notification of detected violations in data that will appear at
the core/FPGA interface several clock cycles later. The exact number of clock cycles that the data is delayed
depends on the skew between the incoming data for the different channels.
Transceiver FPGA/Embedded Core Signals
Table 12 summarizes the interface signals between the FPGA logic and the core. In the table, an input refers to a
signal flowing into the embedded core and an output refers to a signal flowing out of the embedded core.
Table 11. Transceiver Embedded Core/FPGA Interface Signal Description for the ORT42G5
Table 10. Definition of Status Bits of MRWDxx that Vary for Different Channels for the ORT82G5 (Continued)
Channel
Transmit Path Signals
TWDxx[31:0]
TCOMMAxx[3:0]
TBIT9xx[3:0]
TSYS_CLK_xx
TCK78[A:B]
Receive Path Signals
MRWDxx[39:0]
RWCKxx
RCK78[A:B]
RSYS_CLK_A2
RSYS_CLK_B2
CV_SELxx
SYS_RST_N
Index
BC
BC
BD
BD
BA
BA
BB
BB
(xx = [AC, AD, BC or BD])
FPGA/Embedded Core
Interface Signal Name
Bit Index
29
19
29
19
29
19
29
19
CV_BA_OR
SYNC2_B1_OOS
CV_BB_OR
SYNC4_B_OOS
CV_BC_OR
SYNC2_B2_OOS
CV_BD_OR
SYNC8_OOS
Name
Input (I) to or
Output (O)
from Core
O
O
O
O
I
I
I
I
I
I
I
I
Code violation in one or more of the received 10-bit groups for channel BA
Dual channel synchronization of channels BA and BB not successful if 1
Code violation in one or more of the received 10-bit groups for channel BB
Quad channel synchronization of SERDES quad B not successful if 1
Code violation in one or more of the received 10-bit groups for channel BC
Dual channel synchronization of channels BC and BD not successful if 1
Code violation in one or more of the received 10-bit groups for channel BD
Eight channel synchronization not successful if 1
Transmit data – channel xx.
Transmit comma character – channel xx.
Transmit force negative disparity – channel xx
Transmit low-speed clock to the FPGA – channel xx
Transmit low-speed clock to the FPGA – SERDES Quad [A:B].
Receive data – Channel xx (see Table 8 and Table 9).
Low-speed receive clock—Channel xx.
Receive low-speed clock to FPGA—SERDES Quad [A:B].
Low-speed receive FIFO clock for channels AC, AD
Low-speed receive FIFO clock for channels BC, BD
Enable detection of code violations in the incoming data
Synchronous reset of the channel alignment blocks.
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ORCA ORT42G5 and ORT82G5 Data Sheet
Signal Description
Description