ort82g5 Lattice Semiconductor Corp., ort82g5 Datasheet - Page 23

• Manufacturer Part Number: ort82g5
• Description: Xaui And Fc Fpscs
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
alignment will only occur when the communication channel is synchronized. When there is no synchronization of
the link, the 1:4 DEMUX will continue to output 4-byte words at some arbitrary, but constant, boundary.
There are 2 control register bits available for each channel for word alignment. They are DOWDALGN_xx and
NOWDALGN_xx. The DOWDALGN_xx bit is positive edge triggered. Writing a 0 followed by a 1 to this register bit
will cause the corresponding DEMUX to look for a new comma character and align the 32-bit word such that the
comma is in the most significant byte position. It is important that the comma is in the most significant byte position
since the multi-channel aligner looks for comma in the most significant byte only.
Typically, it is not necessary to set the DOWDALGN_xx bit. When the link state machine loses synchronization
(DEMUXWAS_xx register bit is 0), the DEMUX block automatically looks for a new comma character irrespective of
whether the DOWDALGN_xx bit is set or not. However, as discussed earlier, the comma character may become
misaligned without the Fibre Channel link state machine indicating a loss of synchronization. In such cases, the
DOWDALGN_xx bit must be toggled to force resynchronization.
The NOWDALGN_xx bit is a level-sensitive bit. If it is a 1, then the DEMUX does not dynamically alter the word
boundary based on comma and SWDSYNC_xx output of the SERDES. This might be useful if a channel were con-
figured to bypass the multi-channel alignment FIFO and raw 40-bits of data are directed from SERDES to FPGA.
In Fibre Channel mode, the default setting (NOWDALGN_xx = 0) causes the word boundary to be set as soon as
the SERDES SWDSYNC_xx output is a 1 and a comma character has been detected. The character that is the
comma becomes the most-significant portion of the demultiplexed word. When the SERDES loses link synchroni-
zation it will drop SWDSYNC_xx low. The DEMUX will begin search for word alignment as soon as SWDSYNC_xx
goes to 1 again.
The DEMUX passes on to the channel alignment FIFO block a set of control signals that indicate the location of the
synchronizing event. RALIGN_xx[3:0] are these indicators. If there is no link synchronization, all of the
RALIGN_xx[[3:0] bits will be zeros independent of synchronizing events that come in. When the link is synchro-
nized, then the bit that corresponds to the time of the synchronization event will be set to a 1.
The relationship between a time sequence of values input at SRBDxx[7:0] to the values output at RWD_xx[39:0] is
shown in Figure 8. A parallel relationship exists between SRBDx[8] and RWBIT8_xx[3:0] as well as between
SRBD_xx[9] and RWBIT9_xx[3:0].
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