ort82g5 Lattice Semiconductor Corp., ort82g5 Datasheet - Page 49

• Manufacturer Part Number: ort82g5
• Description: Xaui And Fc Fpscs
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 31. Clocking for Eight Channel Alignment
Reset Operation
The SERDES block can be reset in one of three different ways as follows: on power up, using the hardware reset,
or via the microprocessor interface. The power up reset process begins when the power supply voltage ramps up to
approximately 80% of the nominal value of 1.5V. Following this event, the device will be ready for normal operation
after 3 ms.
A hardware reset is initiated by making the PASB_RESETN low for at least two microprocessor clock cycles. The
device will be ready for operation 3 ms after the low to high transition of the PASB_RESETN. This reset function
affects all SERDES channels and resets all microprocessor and internal registers and counters.
Using the software reset option, each channel can be individually reset by setting SWRST (bit 2) to a logic 1 in the
channel configuration register. The device will be ready 3 ms after the SWRST bit is deasserted. Similarly, all four
channels per quad SERDES can be reset by setting the global reset bit GSWRST. The device will be ready for nor-
mal operation 3 ms after the GSWRST bit is deasserted. Note that the software reset option resets only SERDES
internal registers and counters. The microprocessor registers are not affected. It should also be noted that the
embedded block cannot be accessed until after FPGA configuration is complete.
All Clocks at
78.125 MHz
FPGA
Logic
RSYS_CLK_A1
TSYS_CLK_AA
TSYS_CLK_AB
TSYS_CLK_AD
TSYS_CLK_BB
TSYS_CLK_BD
TSYS_CLK_BC
TSYS_CLK_AC
RSYS_CLK_A2
RSYS_CLK_B1
TSYS_CLK_BA
RSYS_CLK_B2
RWCKAA
RWCKAB
RWCKAC
RWCKAD
RWCKBA
RWCKBB
RWCKBC
RWCKBD
RCK78A
RCK78B
TCK78A
TCK78A
TCK78B
Common Logic, Quad A
Common Logic, Quad B
Channel AC
Channel AD
Channel BC
Channel BD
Channel AA
Channel AB
Channel BA
Channel BB
49
ORCA ORT42G5 and ORT82G5 Data Sheet
REFCLK[P:N]_A
REFCLK[P:N]_B
2
2
156.25 MHz
Channels of 3.125
Eight Bidirectional
Gbps Serial Data