ort82g5 Lattice Semiconductor Corp., ort82g5 Datasheet - Page 45

• Manufacturer Part Number: ort82g5
• Description: Xaui And Fc Fpscs
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Table 17. TCK78[A:B] Source Selection
Recommended Transmit Clock Distribution for the ORT82G5
As an example of the recommended clock distribution approach, TSYS_CLK_A[A:D] can be sourced by TCK78A
as shown in Figure 25 if the transmit line rate are common for all four channels in a quad. Similar clocking would be
used for Quad B.
Figure 25. Transmit Clocking for a Single Block (Similar Connections Would Be Used for Block B)
If the transmit line rate is mixed between half and full rate among the channels, then the scheme shown in
Figure 26 can be used. The figure shows TSYS_CLK_AA and TSYS_CLK_AB being sourced by TCK78A and
TSYS_CLK_AC and TSYS_CLK_AD being sourced by TCK78A/2 (the division is done in FPGA logic). Similar
clocking would be used for Quad B.
All Clocks at
78.125 MHz
FPGA
Logic
TSYS_CLK_AB
TSYS_CLK_AA
TSYS_CLK_AD
TSYS_CLK_AC
TCK78A
TCKSEL0
0
1
0
1
Common Logic, Quad A
Channel AC
Channel AD
Channel AA
Channel AB
TCKSEL1
45
0
0
1
1
ORCA ORT42G5 and ORT82G5 Data Sheet
2
Outgoing Serial Data
Clock Source
Four Channels of
REFCLK[P:N]_A
156.25 MHz
Channel C
Channel D
Channel A
Channel B
3.125 Gbps