ort82g5 Lattice Semiconductor Corp., ort82g5 Datasheet - Page 16

• Manufacturer Part Number: ort82g5
• Description: Xaui And Fc Fpscs
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Transmit Path (FPGA to Backplane) Logic
The transmitter section accepts four groups of either 8-bit unencoded data or 10-bit encoded data at the parallel
interface to the FPGA logic. It also uses the reference clock, REFCLK[P:N]_[A:B] to synthesize an internal high-
speed serial bit clock. The serialized transmitted data are available at the differential CML output pins to drive either
an optical transmitters, coaxial media or a circuit board backplane.
As shown in Figure 3, the basic blocks in the transmit path include:
Embedded Core/FPGA interface and 4:1 multiplexer
• Low speed parallel core/FPGA interface
• 4:1 multiplexer
Transmit SERDES
• 8b/10b Encoder
• 10:1 Multiplexer
• CML Output Buffer
Detailed descriptions of the logic blocks are given in following sections. Detailed descriptions of transmit clock dis-
tribution, including the transmit PLL are given in later sections of this data sheet.
Figure 3. Basic Logic Blocks, Transmit Path, Single Channel (Typical Reference Clock Frequency)
TCOMMAxx[3:0]
TSYS_CLK_xx
TWDxx[31:0]
FPGA
TBIT9xx[3:0]
Logic
TCK78[A:B]
78.125 MHz
32
4
4
MUX
Interface and MUX Block
FIFO
TCKSEL[0:1][A:B]
÷
{
4
4:1 MUX
From other channel
or channels
(x9)
For ORT42G5: xx = [AC, AD, BC or BD]
For ORT82G5: xx = [AA, AB, ... BD]
Logic Common to Block
From Control
Register
STBD_xx[7:0]
Force-ve disparity
STBD_xx[9]
STBD_xx[8]
STBC311_xx
8-bit data
K-control
312.5 MHz
16
8
To other
channel or
channels
ORCA ORT42G5 and ORT82G5 Data Sheet
Encoder
bypass)
8B/10B
PLL
(with
{
TX SERDES Block
MUX
10:1
emphasis
Buffer
with Pre-
CML
Buffer
CML
REFCLKP_[A:B]
REFCLKN_[A:B]
HDOUTP_xx
HDOUTN_xx
Backplane
156.25 MHz
Serial
Link