ort82g5 Lattice Semiconductor Corp., ort82g5 Datasheet - Page 52

• Manufacturer Part Number: ort82g5
• Description: Xaui And Fc Fpscs
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Test Modes
In addition to the operational logic described in the preceding sections, the Embedded Core contains logic to sup-
port various test modes - both for device validation and evaluation and for operating system level tests. The follow-
ing sections discuss two of the test support logic blocks, supporting various loopback modes and SERDES
characterization.
Loopback Testing
Loopback testing is performed by looping back (either internal to the Embedded Core, by configuring the FPGA
logic or by external connections) transmitted data to the corresponding receiver inputs, or received data to the
transmitter output. The loopback path may be either serial or parallel.
In general, loopback tests can be classified as “near end” or “far end.” In “near end” loopback (Figure 32(a)), data is
generated and checked locally, i.e. by logic on, or connection of, test equipment to the same card as the FPSC. In
“far end” loopback (Figure 32(b)), the generating and checking functions are performed remotely, either by test
equipment or a remote system card.
Figure 32. “Near End” vs. “Far End” Loopback
The loopback mode can also be characterized by the physical location of the loopback connection. There are three
possible loopback modes supported by the Embedded Core logic:
• High-speed serial loopback at the CML buffer interface (near end)
• Parallel loopback at the SERDES boundary (far end)
Non-Functional
Local System
(to Logic on
or Logic on Local
Test Equipment
Active
(a) “Near End” Loopback
Card)
(b) “Far End” Loopback
System Card
n
m
Device Under Test (DUT)
TCOMMAxx[3:0]
FPGA Logic
MRWDxx[39:0]
TWDxx[31:0]
TBIT9xx[3:0]
{
Generation
Checking
Transmit
32
4
4
Receive
Data
Data
40
Embedded Core
MUX
DE
m
n
Device Under Test (DUT)
FPGA Logic
8B/10B
8B/10B
TCOMMAxx[3:0]
MRWDxx[39:0]
TWDxx[31:0]
TBIT9xx[3:0]
52
SERDES
SERDES
ORCA ORT42G5 and ORT82G5 Data Sheet
SERDES Block
Serial Loopback
Connection
Loopback
High Speed
Connection
Parallel
Buffer
Buffer
Receive
Transmit
CML
CML
32
4
4
40
HDOUT[P:N]_xx
HDIN[P:N]_xx
2
2
Embedded Core
Generation
Checking
Buffer
Buffer
CML
CML
Data
Data
HDOUT[P:N]_xx
HDIN[P:N]_xx
Measurement or
(to Eye Diagram
remote System
Non-Functional
{
2
Active
Card)
2