ort82g5 Lattice Semiconductor Corp., ort82g5 Datasheet - Page 14

• Manufacturer Part Number: ort82g5
• Description: Xaui And Fc Fpscs
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 2. Top Level Block Diagram, Embedded Core Logic (Channel AC)
The Embedded Core provides transceiver functionality for four or eight serial data channels and is organized into
two blocks, each supporting two or four channels. Each channel is identified by both a block identifier [A:B] and a
channel identifier [A:D]. In the ORT42G5 only the channel identifiers C and D are used. (This naming convention
follows that of the ORT82G5).
The data channels can operate independently or they can be combined together (aligned) to achieve higher bit
rates. The mode operation of the core is defined by a set of control registers, which can be written through the sys-
tem bus interface. Also, the status of the core is stored in a set of status registers, which can be read through the
system bus interface.
The transmitter section for each channel accepts 40 bits of data or 32 bits of data and eight control/status bits from
the FPGA logic and optionally encodes the data using 8b/10b encoding. It also accepts the low-speed reference
clock at the REFCLK input and uses this clock to synthesize the internal high-speed serial bit clock. The data is
then serialized and the serialized data are available at the differential CML output terminated in 86 Ω to drive either
an optical transmitter or coaxial media or circuit board/backplane.
The receiver section receives high-speed serial data at its differential CML input port. These data are fed to the
clock recovery section which generates a recovered clock and retimes the data. The retimed data are also deseri-
alized and optionally 8b/10b decoded. The receiver also optionally recognizes the comma characters or code viola-
tions and aligns the bit stream to the proper word boundary. The resulting parallel data is optionally passed to the
multi-channel alignment block before it is presented to the FPGA logic.
8b/10b Encoding and Decoding
In 8b/10b mode, the FPGA logic will receive/transmit 32 bits of data and 4 K_CTRL bits from/to the embedded
core. In the transmit direction, four additional input bits force a negative disparity present state. The embedded core
logic will encode the data to or decode the data from a 10-bit format according to the FC-PH ANSI X3.230:1994
standard (which is also the encoding used by the IEEE 802.3ae Ethernet standard). This encoding/decoding
scheme also allows for the transmission of special characters and supports error detection.
FPGA
Logic
TCOMMAC[3:0]
TSYS_CLK_AC
MRWDAC[39:0]
RSYS_CLK_A2
TWDAC[31:0]
CV_SELAC
RWCKAC
RCK78A
TCK78A
.
.
.
Alignment
2:1 MUX
Channel
Multi -
Block
(x40)
Interface and
MUX Block
Common Logic, Block A
Last Channel (BD)
Next Channel
DEMUX
Block
.
. .
14
Link State
Receive Channel AC
Transmit Channel AC
Machine
ORCA ORT42G5 and ORT82G5 Data Sheet
TX SERDES
DES Block
Block
RX SER-
HDOUT[P:N]_AC
HDIN[P:N]_AC
REFCLK[P:N]_A
2
2
2
Backplane
Serial
Links