ort82g5 Lattice Semiconductor Corp., ort82g5 Datasheet - Page 87

• Manufacturer Part Number: ort82g5
• Description: Xaui And Fc Fpscs
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Package Information
Package Pinouts
Table 43 provides the number of user-programmable I/Os available for each package.
Table 43. I/O Summary
Table 44 and Table 45 provide the package pin and pin function for the ORT42G5 and ORT82G5 FPSC and pack-
ages. The bond pad name is identified in the PIO nomenclature used in the ispLEVER System software design edi-
tor. The Bank column provides information as to which output voltage level bank the given pin is in. The Group
column provides information as to the group of pins the given pin is in. This is used to show which VREF pin is used
to provide the reference voltage for single-ended limited-swing I/Os. If none of these buffer types (such as SSTL,
GTL, HSTL) are used in a given group, then the VREF pin is available as an I/O pin.
When the number of FPGA bond pads exceeds the number of package pins, bond pads are unused. When the
number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects).
When a package pin is to be left as a no connect for a specific die, it is indicated as a note in the device column for
the FPGA. The tables provide no information on unused pads.
As shown in the pair columns in Table 38, differential pairs and physical locations are numbered within each bank
(e.g., L19C-A0 is the nineteenth pair in an associated bank). A ‘C’ indicates complementary differential, whereas a
‘T’ indicates true differential. An _A0 indicates the physical location of adjacent balls in either the horizontal or ver-
tical direction. Other physical indicators are as follows:
• _A1 indicates one ball between pairs.
• _A2 indicates two balls between pairs.
• _D0 indicates balls are diagonally adjacent.
• _D1 indicates balls are diagonally adjacent, separated by one physical ball.
V
(e.g., VREF_TL_01 is the V
REF
pins, shown in the Pin Description columns in Table 44 and Table 45, are associated to the bank and group
User programmable I/O
Available programmable differential pair pins
FPGA configuration pins
FPGA dedicated function pins
Core function pins
VDD15
VDD33
VDDIO
VSS
VDDGB
VDDIB
VDDOB
VDD_ANA
No connect
Total package pins
REF
for group one of the Top Left (TL) bank.
Device
87
ORCA ORT42G5 and ORT82G5 Data Sheet
ORT42G5
204
166
112
484
32
49
34
22
7
2
8
2
4
8
0
ORT82G5
372
330
680
71
63
10
32
91
12
7
2
2
8
8
2