ort82g5 Lattice Semiconductor Corp., ort82g5 Datasheet - Page 37

• Manufacturer Part Number: ort82g5
• Description: Xaui And Fc Fpscs
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Table 12. Transceiver Embedded Core/FPGA Interface Signal Description for the ORT82G5
Reference Clocks and Internal Clock Distribution
Reference Clock Requirements
There are two pairs of reference clock inputs on the ORT42G5 and ORT82G5. The differential reference clock is
distributed to all channels in a block. Each channel has a differential buffer to isolate the clock from the other chan-
nels. The input clock is preferably a differential signal; however, the device can operate with a single-ended input.
The input reference clock directly impacts the transmit data eye, so the clock should have low jitter. In particular, jit-
ter components in the DC to 5 MHz range should be minimized. The required electrical characteristics for the refer-
ence clock are given in Table 38.
Note: In sections of this data sheet, the differential clocks are simply referred to as the reference clock as
REFCLK_[A:B].
Synthesized and Recovered Clocks
The SERDES Embedded Core block contains its own dedicated PLLs for transmit and receive clock generation.
The user provides a reference clock of the appropriate frequency, as described in the previous section. The trans-
mitter PLL uses the REFCLK_[A,B] inputs to synthesize the internal high-speed serial bit clocks. The receiver PLLs
extract the clock from the serial input data and retime the data with the recovered clock.
The receive PLL for each channel has two modes of operation - lock to reference and lock to data with retiming.
When no data or invalid data is present on the HDINP_xx and HDINN_xx pins, the receive VCO will not lock to data
and its frequency can drift outside of the nominal ±350 ppm range. Under this condition, the receive PLL will lock to
REFCLK_[A,B] for a fixed time interval and then will attempt to lock to receive data. The process of attempting to
lock to data, then locking to clock will repeat until valid input data exists. There is also a control register bit per
channel to force the receive PLL to always lock to the reference clock.
The high-speed transmit and receive serial data links can run at 0.6 to 3.7 Gbps, depending on the frequency of the
reference clock and the state of the control bits from the internal transmit control register. The interface to the seri-
alizer/deserializer block runs at 1/10th the bit rate of the data lane. Additionally, the MUX/DEMUX logic converts the
Transmit Path Signals
TWDxx[31:0]
TCOMMAxx[3:0]
TBIT9xx[3:0]
TSYS_CLK_xx
TCK78[A:B]
Receive Path Signals
MRWDxx[39:0]
RWCKxx
RCK78[A:B]
RSYS_CLK_A1
RSYS_CLK_A2
RSYS_CLK_B1
RSYS_CLK_B2
CV_SELxx
SYS_RST_N
xx=... line remain (xx = [AA, ..., BD]
FPGA/Embedded Core
Interface Signal Name
Output (O) from
Input (I) to or
Core
O
O
O
O
I
I
I
I
I
I
I
I
I
I
Transmit data – channel xx.
Transmit comma character – channel xx.
Transmit force negative disparity – channel xx
Transmit low-speed clock to the FPGA – channel xx
Transmit low-speed clock to the FPGA – SERDES Quad [A:B].
Receive data – Channel xx (see Table 8 and Table ).
Low-speed receive clock—Channel xx.
Receive low-speed clock to FPGA—SERDES Quad [A:B].
Low-speed receive FIFO clock for channels AA, AB
Low-speed receive FIFO clock for channels AC, AD
Low-speed receive FIFO clock for channels BA, BB
Low-speed receive FIFO clock for channels BC, BD
Enable detection of code violations in the incoming data
Synchronous reset of the channel alignment blocks.
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ORCA ORT42G5 and ORT82G5 Data Sheet
Signal Description