ort82g5 Lattice Semiconductor Corp., ort82g5 Datasheet - Page 50

• Manufacturer Part Number: ort82g5
• Description: Xaui And Fc Fpscs
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Start Up Sequence for the ORT42G5
The following sequence is required by the ORT42G5 device. For information required for simulation that may be dif-
ferent than this sequence, see the ORT42G5 Design Kit.
1. Initiate a hardware reset by making PASB_RESETN low. Keep this low during FPGA configuration of the
2. At startup, the legacy SERDES channel logic must be powered down and removed from any multi-channel
3. Configure the following SERDES internal and external registers. Note that after device initialization, all alarm
4. If 8b/10b mode is enabled, enable link synchronization by periodically sending the following sequence three
Set the following bits in register 30800:
device. The device will be ready for operation 3 ms after the low to high transition of PASB_RESETN.
alignment groups:
• Setting bit 1 to one in registers at locations 30002, 30012, 30102, 30112, 30003, 30013, 30103 and 30113
• Setting bits 4 and 5 to zero (reset condition) in the register at locations 30810 and 30910 removes the legacy
and status bits should be read once to clear them. A subsequent read will provide the valid state.
– Bits LCKREFN_[AC and AD] to 1, which implies lock to data.
– Bits ENBYSYNC_[AC and AD] to 1 which enables dynamic alignment to comma.
Set the following bits in register 30801:
– Bits LOOPENB_[AC and AD] to 1 if high-speed serial loopback is desired.
Set the following bits in register 30900:
– Bits LCKREFN_[BC and BD] to 1 which implies lock to data.
– Bits ENBYSYNC_[BC and BD] to 1 which enables dynamic alignment to comma.
Set the following bits in register 30901:
– Bits LOOPENB_[BC and BD] to 1 if high-speed serial loopback is desired.
Set the following bits in registers 30022, 30032, 30122, 30132:
– TXHR set to 1 if TX half-rate is desired.
– 8b10bT set to 1 if 8b10b encoding is desired.
Set the following bits in registers 30023, 30033, 30123, 30133:
– RXHR Set to 1 if RX half-rate is desired.
– 8b10bR set to 1 if 8b10b decoding is desired.
– LINKSM set to 1 if the Fibre Channel state machine is desired.
Assert GSWRST bit by writing 1’s to both SERDES blocks. Deassert GSWRST bit by writing 0’s to both SER-
DES blocks. Wait 3 ms. If higher speed serial loopback has been selected, the receive PLLs will use this time
to lock to the new serial data.
Monitor the following alarm bits in registers 30020, 30030, 30120, 30130:
– LKI, PLL lock indicator. 1 indicates that PLL has achieved lock.
times:
– K28.5 D21.4 D21.5 D21.5 or any other idle ordered set (starting with a /comma/) in FC mode.
– /comma/ characters for the XAUI state machine and /A/ characters for word and channel alignment in XAUI
mode.
powers down the legacy logic. (Note that the reset value for these bits is 0.)
logic from any alignment group.
50
ORCA ORT42G5 and ORT82G5 Data Sheet