MC68HC912D60 Motorola, MC68HC912D60 Datasheet - Page 172

• Manufacturer Part Number: MC68HC912D60
• Description: Microcontrollers
• Manufacturer: Motorola

Clock Functions
Technical Data
172
CR2
1. Time for writing $55 following previous COP restart of time-out logic due to writing $AA.
2. Please refer to WCOP bit description above.
3. Window COP cannot be used at this rate.
0
0
0
0
1
1
1
1
CR1
0
0
1
1
0
0
1
1
CR0
0
1
0
1
0
1
0
1
X clock
Divide
OFF
2
2
2
2
2
2
2
by
13
15
17
19
21
22
23
DISR — Disable Resets from COP Watchdog and Clock Monitor
CR2, CR1, CR0 — COP Watchdog Timer Rate select bits
Writes are not allowed in normal modes, anytime in special modes.
Read anytime.
These bits select the COP time-out rate. The clock used for this
module is the XCLK.
Write once in normal modes, anytime in special modes. Read
anytime.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = Normal operation.
1 = Regardless of other control bit states, COP and clock monitor
1.048576 ms -0/+1.024 ms
Table 11-5. COP Watchdog Rates
262.144 ms -0/+1.024 ms
524.288 ms -0/+1.024 ms
16.384 ms -0/+0.256 ms
65.536 ms -0/+1.024 ms
1.024 ms -0/+0.256 ms
4.096 ms -0/+0.256 ms
will not generate a system reset.
8.0 MHz X clock.
Go to: www.freescale.com
Time-out
OFF
Clock Functions
Window start
196.608 ms
393.216 ms
786.432 ms
12.288 ms
49.152 ms
0.768 ms
3.072 ms
OFF
(1)
Window COP enabled:
Window end
261.120 ms
523.264 ms
MC68HC912D60A — Rev 3.0
1.047552 s
16.128 ms
64.512 ms
0.768 ms
3.840 ms
OFF
Window
MOTOROLA
Effective
18.8 %
23.4 %
23.4 %
24.6 %
24.8 %
24.9 %
0 %
OFF
(3)
(2)