MC68HC912D60 Motorola, MC68HC912D60 Datasheet - Page 354
MC68HC912D60
Manufacturer Part Number
MC68HC912D60
Description
Microcontrollers
Manufacturer
Motorola
Datasheet
1.MC68HC912D60.pdf
(460 pages)
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Analog-to-Digital Converter
18.5 ATD Operational Modes
18.5.1 Power Down Mode
Technical Data
354
programmable constant in order to generate the ATD module’s internal
clock. One additional benefit of the prescaled clock feature is that it
allows the user further control over the sample period (note that
changing the module clock also affects conversion time).
The prescaler is based on a 5 bit modulus counter and divides the PCLK
by an integer value between 1 and 32. The final clock frequency is
obtained with a further division by 2.
The internal ATD module clock and the system PCLK have a direct
phase relationship, however the ATD module operates as if it is
effectively asynchronous to MCU bus clock cycles.
The ATD module can be powered down under program control. This is
done by turning the clock signals off to the digital electronics of the
module and eliminating the quiescent current draw of the analog
electronics.
Power down control is implemented in one of three ways.
Note that the reset default for the ADPU bit is zero. Therefore, when this
module is reset, it is reset into the power down state.
Once the command to power down has been received, the ATD module
aborts any conversion sequence in progress and enters lower power
mode. When the module is powered up again, the bias settings in the
analog electronics must be given time to stabilize before conversions
1. Using the ADPU bit in control register ATDCTL2.
2. When STOP instruction is executed, the module will power down
3. If the module WAIT enable bit (ASWAI) is set and a WAIT
Freescale Semiconductor, Inc.
For More Information On This Product,
for the duration of the STOP function.
instruction is executed, the module will power down for the
duration of the WAIT function.
Analog-to-Digital Converter
Go to: www.freescale.com
MC68HC912D60A — Rev 3.0
MOTOROLA
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