MC68HC912D60 Motorola, MC68HC912D60 Datasheet - Page 240
MC68HC912D60
Manufacturer Part Number
MC68HC912D60
Description
Microcontrollers
Manufacturer
Motorola
Datasheet
1.MC68HC912D60.pdf
(460 pages)
- Current page: 240 of 460
- Download datasheet (4Mb)
Enhanced Capture Timer
Technical Data
240
RDPT — Timer Port Drive Reduction
TCRE — Timer Counter Reset Enable
PR2, PR1, PR0 — Timer Prescaler Select
This bit reduces the effective output driver size which can reduce
power supply current and generated noise depending upon pin
loading.
This bit allows the timer counter to be reset by a successful output
compare 7 event. This mode of operation is similar to an up-counting
modulus counter.
If TC7 = $0000 and TCRE = 1, TCNT will stay at $0000 continuously.
If TC7 = $FFFF and TCRE = 1, TOF will never be set when TCNT is
reset from $FFFF to $0000.
These three bits specify the number of ÷2 stages that are to be
inserted between the module clock and the main timer counter.
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = Normal output drive capability
1 = Enable output drive reduction function
0 = Counter reset inhibited and counter free runs
1 = Counter reset by a successful output compare 7
Go to: www.freescale.com
Enhanced Capture Timer
PR2
0
0
0
0
1
1
1
1
Table 14-3. Prescaler Selection
PR1
0
0
1
1
0
0
1
1
PR0
0
1
0
1
0
1
0
1
Prescale
MC68HC912D60A — Rev 3.0
Factor
128
16
32
64
1
2
4
8
MOTOROLA
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