MC68HC912D60 Motorola, MC68HC912D60 Datasheet - Page 33

• Manufacturer Part Number: MC68HC912D60
• Description: Microcontrollers
• Manufacturer: Motorola

2.4 Data Types
2.5 Addressing Modes
MC68HC912D60A — Rev 3.0
MOTOROLA
Condition Code Register (CCR) contains five status indicators, two
interrupt masking bits, and a STOP disable bit. The five flags are half
carry (H), negative (N), zero (Z), overflow (V), and carry/borrow (C). The
half-carry flag is used only for BCD arithmetic operations. The N, Z, V,
and C status bits allow for branching based on the results of a previous
operation.
After a reset, the CPU fetches a vector from the appropriate address and
begins executing instructions. The X and I interrupt mask bits are set to
mask any interrupt requests. The S bit is also set to inhibit the STOP
instruction.
The CPU12 supports the following data types:
A byte is eight bits wide and can be accessed at any byte location. A
word is composed of two consecutive bytes with the most significant
byte at the lower value address. There are no special requirements for
alignment of instructions or operands.
Addressing modes determine how the CPU accesses memory locations
to be operated upon. The CPU12 includes all of the addressing modes
of the M68HC11 CPU as well as several new forms of indexed
addressing.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Bit data
8-bit and 16-bit signed and unsigned integers
16-bit unsigned fractions
16-bit addresses
Table 2-1
Go to: www.freescale.com
Central Processing Unit
is a summary of the available addressing modes.
Central Processing Unit
Technical Data
Data Types
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