MC68HC912D60 Motorola, MC68HC912D60 Datasheet - Page 208
MC68HC912D60
Manufacturer Part Number
MC68HC912D60
Description
Microcontrollers
Manufacturer
Motorola
Datasheet
1.MC68HC912D60.pdf
(460 pages)
- Current page: 208 of 460
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Pulse Width Modulator
Technical Data
208
(ECLK or Scaled ECLK)
CLOCK SOURCE
PWENx
(CLOCK EDGE SYNC)
GATE
SYNC
Figure 13-1. Block Diagram of PWM Left-Aligned Output Channel
PPOL = 0
PPOL = 1
possible to know where the count is with respect to the duty value and
software can be used to make adjustments by turning the enable bit off
and on.
The four PWM channel outputs share general-purpose port P pins.
Enabling PWM pins takes precedence over the general-purpose port.
When PWM channels are not in use, the port pins may be used for
discrete input/output.
RESET
Freescale Semiconductor, Inc.
For More Information On This Product,
PWCNTx
PWDTY
Go to: www.freescale.com
Pulse Width Modulator
UP/DOWN
8-BIT COMPARE =
8-BIT COMPARE =
CENTR = 0
PWDTYx
PWPERx
PWPER
S
R
Q
Q
PPOLx
MUX
DATA REGISTER
FROM PORT P
MC68HC912D60A — Rev 3.0
MUX
DRIVER
TO PIN
MOTOROLA
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