MC68HC912D60 Motorola, MC68HC912D60 Datasheet - Page 247
MC68HC912D60
Manufacturer Part Number
MC68HC912D60
Description
Microcontrollers
Manufacturer
Motorola
Datasheet
1.MC68HC912D60.pdf
(460 pages)
- Current page: 247 of 460
- Download datasheet (4Mb)
PACN1, PACN0 — Pulse Accumulators Count Registers
MCCTL — 16-Bit Modulus Down-Counter Control Register
MC68HC912D60A — Rev 3.0
MOTOROLA
RESET:
RESET:
$00A4
$00A5
BIT 7
BIt 7
Bit 7
BIT 7
MCZI
0
0
MODMC
6
6
6
0
6
0
Read: any time
Write: any time
The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form
the PACB 16-bit pulse accumulator. When PACB in enabled, (PBEN=1
in PBCTL, $B0) the PACN1 and PACN0 registers contents are
respectively the high and low byte of the PACB.
When PACN1 overflows from $FF to $00, the Interrupt flag PBOVF in
PBFLG ($B1) is set.
Full count register access should take place in one clock cycle. A
separate read/write for high byte and low byte will give a different result
than accessing them as a word.
Read: any time
Write: any time
MCZI — Modulus Counter Underflow Interrupt Enable
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = Modulus counter interrupt is disabled.
1 = Modulus counter interrupt is enabled.
RDMCL
5
5
5
0
5
0
Go to: www.freescale.com
Enhanced Capture Timer
ICLAT
4
4
4
0
4
0
FLMC
3
3
3
0
3
0
MCEN
2
2
2
0
2
0
MCPR1
1
1
1
0
1
0
Enhanced Capture Timer
MCPR0
BIT 0
Bit 0
Bit 0
BIT 0
0
0
Timer Registers
Technical Data
$00A4, $00A5
PACN1 (hi)
PACN0 (lo)
$00A6
247
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