MC68HC912D60 Motorola, MC68HC912D60 Datasheet - Page 442
MC68HC912D60
Manufacturer Part Number
MC68HC912D60
Description
Microcontrollers
Manufacturer
Motorola
Datasheet
1.MC68HC912D60.pdf
(460 pages)
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Appendix: Changes from MC68HC912D60
22.2.7.7 SCF bit
22.2.7.8 ATDTESTx
Technical Data
442
To ensure compatibility, the application should not rely on ongoing
conversions being aborted. Also any interrupts from the completion of an
ongoing sequence should be masked and/or handled correctly.
In SCAN mode (SCAN bit = 1 in ATDxCTL5) the Sequence Complete
Flag (SCF bit in ATDSTATx) is set after completion of each conversion
sequence. Previously it was only set at the end of the first conversion
sequence.
To ensure compatibility the application should not rely on this flag being
set only once per SCAN mode.
Reading the ATDTESTx register in nornal modes returns the value of the
Successive Approximation Register (SAR). Previously it always read as
zero.
The RST bit in the ATDTESTx register can be written in normal modes
(in order to reset the ATD). Previously it was read only.
To ensure compatibility this register should not be read or written to.
Freescale Semiconductor, Inc.
For More Information On This Product,
Appendix: Changes from MC68HC912D60
Go to: www.freescale.com
MC68HC912D60A — Rev 3.0
MOTOROLA
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