MC68HC912D60 Motorola, MC68HC912D60 Datasheet - Page 249
MC68HC912D60
Manufacturer Part Number
MC68HC912D60
Description
Microcontrollers
Manufacturer
Motorola
Datasheet
1.MC68HC912D60.pdf
(460 pages)
- Current page: 249 of 460
- Download datasheet (4Mb)
MCFLG — 16-Bit Modulus Down-Counter FLAG Register
MC68HC912D60A — Rev 3.0
MOTOROLA
RESET:
MCZF
BIT 7
0
6
0
0
MCEN — Modulus Down-Counter Enable
MCPR1, MCPR0 — Modulus Counter Prescaler select
Read: any time
Write: Only for clearing bit 7
MCZF — Modulus Counter Underflow Interrupt Flag
When MCEN=0, the counter is preset to $FFFF. This will prevent an
early interrupt flag when the modulus down-counter is enabled.
These two bits specify the division rate of the modulus counter
prescaler.
The newly selected prescaler division rate will not be effective until a
load of the load register into the modulus counter count register
occurs.
The flag is set when the modulus down-counter reaches $0000.
Writing a1 to this bit clears the flag (if TFFCA=0). Writing zero has no
effect.
Any access to the MCCNT register will clear the MCZF flag in this
register when TFFCA bit in register TSCR($86) is set.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = Modulus counter disabled.
1 = Modulus counter is enabled.
5
0
0
Go to: www.freescale.com
Enhanced Capture Timer
MCPR1
0
4
0
0
0
1
1
POLF3
MCPR0
3
0
0
1
0
1
POLF2
2
0
Prescaler division
rate
16
1
4
8
POLF1
1
0
Enhanced Capture Timer
POLF0
BIT 0
0
Timer Registers
Technical Data
$00A7
249
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