MC68HC912D60 Motorola, MC68HC912D60 Datasheet - Page 332
MC68HC912D60
Manufacturer Part Number
MC68HC912D60
Description
Microcontrollers
Manufacturer
Motorola
Datasheet
1.MC68HC912D60.pdf
(460 pages)
- Current page: 332 of 460
- Download datasheet (4Mb)
MSCAN Controller
17.13.3 msCAN12 Module Control Register 1 (CMCR1).
Technical Data
332
CMCR1
$0101
RESET
R
W
NOTE:
Bit 7
0
0
LOOPB — Loop Back Self Test Mode
WUPM — Wake-Up Mode
CLKSRC — msCAN12 Clock Source
The CMCR1 register can be written only if the SFTRES bit in CMCR0 is
set.
When this bit is set the msCAN12 performs an internal loop back
which can be used for self test operation: the bit stream output of the
transmitter is fed back to the receiver internally. The RxCAN input pin
is ignored and the TxCAN output goes to the recessive state (1). The
msCAN12 behaves as it does normally when transmitting and treats
its own transmitted message as a message received from a remote
node. In this state the msCAN12 ignores the bit sent during the ACK
slot of the CAN frame acknowledge field to insure proper reception of
its own message. Both transmit and receive interrupts are generated.
This flag defines whether the integrated low-pass filter is applied to
protect the msCAN12 from spurious wake-ups (see
Wake-Up
This flag defines which clock source the msCAN12 module is driven from
(only for system with CGM module; see
Freescale Semiconductor, Inc.
6
0
0
For More Information On This Product,
0 = Normal operation
1 = Activate loop back self test mode
0 = msCAN12 will wake up the CPU after any recessive to
1 = msCAN12 will wake up the CPU only in the case of dominant pulse
0 = The msCAN12 clock source is EXTALi.
1 = The msCAN12 clock source is SYSCLK, twice the frequency of
dominant edge on the CAN bus.
on the bus which has a length of at least approximately T
ECLK.
Go to: www.freescale.com
Function).
5
0
0
MSCAN Controller
4
0
0
3
0
0
Clock
LOOPB
2
0
MC68HC912D60A — Rev 3.0
System,
WUPM
Programmable
1
0
Figure
MOTOROLA
17-7).
CLKSRC
wup
Bit 0
0
.
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