MC68HC912D60 Motorola, MC68HC912D60 Datasheet - Page 333

• Manufacturer Part Number: MC68HC912D60
• Description: Microcontrollers
• Manufacturer: Motorola

17.13.4 msCAN12 Bus Timing Register 0 (CBTR0)
MC68HC912D60A — Rev 3.0
MOTOROLA
CBTR0
$0102
RESET
R
W
NOTE:
SJW1
Bit 7
0
SJW1, SJW0 — Synchronization Jump Width
BRP5 – BRP0 — Baud Rate Prescaler
The CBTR0 register can only be written if the SFTRES bit in CMCR0 is
set.
SJW0
The synchronization jump width defines the maximum number of time
quanta (Tq) clock cycles by which a bit may be shortened, or
lengthened, to achieve resynchronization on data transitions on the
bus (see
These bits determine the time quanta (Tq) clock, which is used to
build up the individual bit timing, according to
Freescale Semiconductor, Inc.
6
0
BRP5
For More Information On This Product,
0
0
0
0
1
:
:
SJW1
0
0
1
1
Table
BRP5
BRP4
Go to: www.freescale.com
5
0
Table 17-5. Synchronization jump width
0
0
0
0
1
:
:
MSCAN Controller
17-5).
Table 17-6. Baud rate prescaler
BRP3
BRP4
0
0
0
0
1
:
:
4
0
SJW0
0
1
0
1
BRP2
0
0
0
0
1
:
:
BRP3
3
0
Programmer’s Model of Control Registers
BRP1
0
0
1
1
1
:
:
Synchronization jump width
BRP2
2
0
BRP0
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
1 Tq clock cycle
0
1
0
1
1
:
:
Table
Prescaler value
BRP1
17-6.
1
0
MSCAN Controller
Technical Data
(P)
64
1
2
3
4
:
:
BRP0
Bit 0
0
333