MC68HC912D60 Motorola, MC68HC912D60 Datasheet - Page 402

• Manufacturer Part Number: MC68HC912D60
• Description: Microcontrollers
• Manufacturer: Motorola

Development Support
BRKDH — Breakpoint Data Register, High Byte
BRKDL — Breakpoint Data Register, Low Byte
19.6 Instruction Tagging
Technical Data
402
RESET:
RESET:
Bit 15
Bit 7
Bit 7
Bit 7
0
0
14
6
0
6
6
0
These bits are compared to the most significant byte of the data bus or
the most significant byte of the address bus in dual address modes.
BKEN[1:0], BKDBE, and BKMBH control how this byte will be used in the
breakpoint comparison.
These bits are compared to the least significant byte of the data bus or
the least significant byte of the address bus in dual address modes.
BKEN[1:0], BKDBE, BK1ALE, and BKMBL control how this byte will be
used in the breakpoint comparison.
The instruction queue and cycle-by-cycle CPU activity can be
reconstructed in real time or from trace history that was captured by a
logic analyzer. However, the reconstructed queue cannot be used to
stop the CPU at a specific instruction, because execution has already
begun by the time an operation is visible outside the MCU. A separate
instruction tagging mechanism is provided for this purpose.
Executing the BDM TAGGO command configures two MCU pins for
tagging. The TAGLO signal shares a pin with the LSTRB signal, and the
Freescale Semiconductor, Inc.
For More Information On This Product,
13
5
0
5
5
0
Go to: www.freescale.com
Development Support
12
4
0
4
4
0
11
3
0
3
3
0
10
2
0
2
2
0
MC68HC912D60A — Rev 3.0
1
9
0
1
1
0
Bit 0
Bit 8
Bit 0
Bit 0
0
0
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