MC68HC908AZ32ACFU MOTOROLA [Motorola, Inc], MC68HC908AZ32ACFU Datasheet - Page 102

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MC68HC908AZ32ACFU

Manufacturer Part Number
MC68HC908AZ32ACFU
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet

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Central Processor Unit (CPU)
6.6.1 WAIT mode
6.6.2 STOP mode
6.7 CPU during break interrupts
Advance Information
102
The WAIT instruction:
The STOP instruction:
After exiting STOP mode, the CPU clock begins running after the
oscillator stabilization delay.
If the break module is enabled, a break interrupt causes the CPU to
execute the software interrupt instruction (SWI) at the completion of the
current CPU instruction. See
counter vectors to $FFFC–$FFFD ($FEFC–$FEFD in monitor mode).
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
Freescale Semiconductor, Inc.
For More Information On This Product,
clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from WAIT mode by interrupt, the I
bit remains clear. After exit by reset, the I bit is set.
Disables the CPU clock
clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from STOP mode by
external interrupt, the I bit remains clear. After exit by reset, the I
bit is set.
Disables the CPU clock
Central Processor Unit (CPU)
Go to: www.freescale.com
Section 11. Break
68HC908AZ32A — Rev 0.0
Module. The program
MOTOROLA

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