MC68HC908AZ32ACFU MOTOROLA [Motorola, Inc], MC68HC908AZ32ACFU Datasheet - Page 289

• Manufacturer Part Number: MC68HC908AZ32ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

18.4.4.2 Buffered PWM Signal Generation
68HC908AZ32A — Rev 0.0
MOTOROLA
NOTE:
to be missed. The TIMA may pass the new value before it is written to
the TIMA channel registers.
Use the following methods to synchronize unbuffered changes in the
PWM pulse width on channel x:
In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to self-
correct in the event of software error or noise. Toggling on output
compare also can cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
Channels 0 and 1 can be linked to form a buffered PWM channel whose
output appears on the PTE2/TCH0 pin. The TIMA channel registers of
the linked pair alternately control the pulse width of the output.
Setting the MS0B bit in TIMA channel 0 status and control register
(TASC0) links channel 0 and channel 1. The TIMA channel 0 registers
initially control the pulse width on the PTE2/TCH0 pin. Writing to the
TIMA channel 1 registers enables the TIMA channel 1 registers to
synchronously control the pulse width at the beginning of the next PWM
period. At each subsequent overflow, the TIMA channel registers (0 or
1) that control the pulse width are the ones written to last. TASC0
controls and monitors the buffered PWM function and TIMA channel 1
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When changing to a shorter pulse width, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the
PWM period to write the new value.
When changing to a longer pulse width, enable TIMA overflow
interrupts and write the new value in the TIMA overflow interrupt
routine. The TIMA overflow interrupt occurs at the end of the
current PWM period. Writing a larger value in an output compare
interrupt routine (at the end of the current pulse) could cause two
output compares to occur in the same PWM period.
Timer Interface Module A (TIMA)
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Timer Interface Module A (TIMA)
Functional Description
Advance Information
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