MC68HC908AZ32ACFU MOTOROLA [Motorola, Inc], MC68HC908AZ32ACFU Datasheet - Page 376

• Manufacturer Part Number: MC68HC908AZ32ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

I/O Ports
23.6.2 Data Direction Register D
Advance Information
376
NOTE:
Address:
Data direction register D (DDRD) does not affect the data direction of
port D pins that are being used by the TIMA or TIMB. However, the
DDRD bits always determine whether reading port D returns the states
of the latches or logic 0.
TACLK/TBCLK — Timer Clock Input Bit
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic 1 to a DDRD bit enables the output buffer for
the corresponding port D pin; a logic 0 disables the output buffer.
DDRD[7:0] — Data Direction Register D Bits
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
The PTD6/ATD14/TCLK pin is the external clock input for the TIMA.
The PTD4/ATD12 pin is the external clock input for the TIMB. The
prescaler select bits, PS[2:0], select PTD6/ATD14/TCLK or
PTD4/ATD12 as the TIM clock input. (See
Control Registers
Control Registers
clock, PTD6/ATD14/TCLK
purpose I/O. While TACLK/TBCLK are selected corresponding DDRD
bits have no effect.
These read/write bits control port D data direction. Reset clears
DDRD[7:0], configuring all port D pins as inputs.
For More Information On This Product,
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
DDRD7
$0007
Bit 7
Figure 23-12. Data Direction Register D (DDRD)
0
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DDRD6
6
0
I/O Ports
on page 299 and
on page 328). When not selected as the TIM
DDRD5
5
0
and
DDRD4
PTD4/ATD12 are available for general-
4
0
TIMB Channel Status and
DDRD3
3
0
TIMA Channel Status and
68HC908AZ32A — Rev 0.0
DDRD2
2
0
DDRD1
1
0
MOTOROLA
DDRD0
Bit 0
0