MC68HC908AZ32ACFU MOTOROLA [Motorola, Inc], MC68HC908AZ32ACFU Datasheet - Page 27
MC68HC908AZ32ACFU
Manufacturer Part Number
MC68HC908AZ32ACFU
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908AZ32ACFU.pdf
(468 pages)
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68HC908AZ32A — Rev 0.0
MOTOROLA
15-2 IRQ Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
15-3 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . . 204
16-1 SCI Module Block Diagram
16-2 SCI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
16-3 SCI Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
16-4 SCI Transmitter
16-5 SCI Transmitter I/O Register Summary . . . . . . . . . . . . . . . . . 215
16-6 SCI Receiver Block Diagram
16-7 SCI I/O Receiver Register Summary . . . . . . . . . . . . . . . . . . .219
16-8 Receiver Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
16-9 Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
16-10 Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
16-11 SCI Control Register 1 (SCC1). . . . . . . . . . . . . . . . . . . . . . . . 230
16-12 SCI Control Register 2 (SCC2). . . . . . . . . . . . . . . . . . . . . . . . 233
16-13 SCI Control Register 3 (SCC3). . . . . . . . . . . . . . . . . . . . . . . . 236
16-14 SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . . . . 238
16-15 Flag Clearing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
16-16 SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . . . . 242
16-17 SCI Data Register (SCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
16-18 SCI Baud Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . . . . 243
17-1 SPI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 251
17-2 Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . . . . 252
17-3 Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . 255
17-4 Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . 256
17-5 Transmission Start Delay (Master) . . . . . . . . . . . . . . . . . . . . . 258
17-6 Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . . . . 260
17-7 Clearing SPRF When OVRF Interrupt Is Not Enabled . . . . . . 261
17-8 SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . . . 264
17-9 SPRF/SPTE CPU Interrupt Timing . . . . . . . . . . . . . . . . . . . . . 265
17-10 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
17-11 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . . 272
17-12 SPI Status and Control Register (SPSCR) . . . . . . . . . . . . . . .275
17-13 SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
18-1 TIMA Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
18-2 TIMA I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 282
18-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 288
18-4 TIMA Status and Control Register (TASC) . . . . . . . . . . . . . . .295
18-5 TIMA Counter Registers (TACNTH and TACNTL) . . . . . . . . . 298
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
List of Figures
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
. . . . . . . . . . . . . . . . . . . . . . . . 210
. . . . . . . . . . . . . . . . . . . . . . 218
Advance Information
List of Figures
27
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