MC68HC908AZ32ACFU MOTOROLA [Motorola, Inc], MC68HC908AZ32ACFU Datasheet - Page 274
MC68HC908AZ32ACFU
Manufacturer Part Number
MC68HC908AZ32ACFU
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908AZ32ACFU.pdf
(468 pages)
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Serial Peripheral Interface (SPI)
17.14.2 SPI Status and Control Register
Advance Information
274
SPWOM — SPI Wired-OR Mode Bit
SPE — SPI Enable Bit
SPTIE — SPI Transmit Interrupt Enable Bit
The SPI status and control register contains flags to signal the following
conditions:
The SPI status and control register also contains bits that perform these
functions:
Freescale Semiconductor, Inc.
This read/write bit disables the pullup devices on pins SPSCK, MOSI,
and MISO so that those pins become open-drain outputs.
This read/write bit enables the SPI module. Clearing SPE causes a
partial reset of the SPI (see
clears the SPE bit.
This read/write bit enables CPU interrupt requests generated by the
SPTE bit. SPTE is set when a byte transfers from the transmit data
register to the shift register. Reset clears the SPTIE bit.
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For More Information On This Product,
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
1 = SPI module enabled
0 = SPI module disabled
1 = SPTE CPU interrupt requests enabled
0 = SPTE CPU interrupt requests disabled
Receive data register full
Failure to clear SPRF bit before next byte is received (overflow
error)
Inconsistent logic level on SS pin (mode fault error)
Transmit data register empty
Enable error interrupts
Enable mode fault error detection
Select master SPI baud rate
Serial Peripheral Interface (SPI)
Go to: www.freescale.com
Resetting the SPI
68HC908AZ32A — Rev 0.0
on page 265). Reset
MOTOROLA
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