MC68HC908AZ32ACFU MOTOROLA [Motorola, Inc], MC68HC908AZ32ACFU Datasheet - Page 265

• Manufacturer Part Number: MC68HC908AZ32ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

17.10 Resetting the SPI
68HC908AZ32A — Rev 0.0
MOTOROLA
SPSCK (CPHA:CPOL = 1:0)
WRITE TO SPDR
READ SPSCR
READ SPDR
1
2
3
4
5
6
SPRF
CPU WRITES BYTE 1 TO SPDR, CLEARING
SPTE BIT.
BYTE 1 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
CPU WRITES BYTE 2 TO SPDR, QUEUEING
BYTE 2 AND CLEARING SPTE BIT.
FIRST INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
CPU READS SPSCR WITH SPRF BIT SET.
SPTE
MOSI
Figure 17-9. SPRF/SPTE CPU Interrupt Timing
For a slave, the transmit data buffer allows back-to-back transmissions
to occur without the slave having to time the write of its data between the
transmissions. Also, if no new data is written to the data buffer, the last
value contained in the shift register will be the next data word
transmitted.
Any system reset completely resets the SPI. Partial reset occurs
whenever the SPI enable bit (SPE) is low. Whenever SPE is low, the
following occurs:
1
Freescale Semiconductor, Inc.
For More Information On This Product,
Serial Peripheral Interface (SPI)
MSB BIT
BYTE 1
Go to: www.freescale.com
2
6
BIT
5
3
BIT
4
BIT
3
BIT
2
BIT
1
10
11 CPU READS SPSCR WITH SPRF BIT SET.
12 CPU READS SPDR, CLEARING SPRF BIT.
7
8
9
LSB MSB BIT
5
4
CPU READS SPDR, CLEARING SPRF BIT.
CPU WRITES BYTE 3 TO SPDR, QUEUEING
BYTE 3 AND CLEARING SPTE BIT.
SECOND INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
BYTE 3 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
BYTE 2
6
6
7
BIT
5
8
BIT
4
Serial Peripheral Interface (SPI)
BIT
3
BIT
2
BIT
1
LSB MSB BIT
10
9
Advance Information
BYTE 3
11
Resetting the SPI
6
12
BIT
5
BIT
4
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