MC68HC908AZ32ACFU MOTOROLA [Motorola, Inc], MC68HC908AZ32ACFU Datasheet - Page 317

• Manufacturer Part Number: MC68HC908AZ32ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

19.4.3.2 Buffered Output Compare
68HC908AZ32A — Rev 0.0
MOTOROLA
NOTE:
Channels 0 and 1 can be linked to form a buffered output compare
channel whose output appears on the PTF4 pin. The TIMB channel
registers of the linked pair alternately control the output.
Setting the MS0B bit in TIMB channel 0 status and control register
(TBSC0) links channel 0 and channel 1. The output compare value in the
TIMB channel 0 registers initially controls the output on the PTF4 pin.
Writing to the TIMB channel 1 registers enables the TIMB channel 1
registers to synchronously control the output after the TIMB overflows.
At each subsequent overflow, the TIMB channel registers (0 or 1) that
control the output are the ones written to last. TBSC0 controls and
monitors the buffered output compare function and TIMB channel 1
status and control register (TBSC1) is unused. While the MS0B bit is set,
the channel 1 pin, PTF5/TBCH1, is available as a general-purpose I/O
pin.
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. Writing to the active
channel registers is the same as generating unbuffered output
compares.
Freescale Semiconductor, Inc.
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When changing to a smaller value, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current output compare pulse. The interrupt routine has until
the end of the counter overflow period to write the new value.
When changing to a larger output compare value, enable TIMB
overflow interrupts and write the new value in the TIMB overflow
interrupt routine. The TIMB overflow interrupt occurs at the end of
the current counter overflow period. Writing a larger value in an
output compare interrupt routine (at the end of the current pulse)
could cause two output compares to occur in the same counter
overflow period.
Timer Interface Module B (TIMB)
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Timer Interface Module B (TIMB)
Functional Description
Advance Information
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