MC68HC908AZ32ACFU MOTOROLA [Motorola, Inc], MC68HC908AZ32ACFU Datasheet - Page 201
MC68HC908AZ32ACFU
Manufacturer Part Number
MC68HC908AZ32ACFU
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908AZ32ACFU.pdf
(468 pages)
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68HC908AZ32A — Rev 0.0
MOTOROLA
$001A
Addr.
IRQ Status/Control Register (ISCR)
NOTE:
Register Name
When an interrupt pin is both falling-edge and low-level-triggered, the
interrupt latch remains set until both of the following occur:
The vector fetch or software clear may occur before or after the interrupt
pin returns to logic 1. As long as the pin is low, the interrupt request
remains pending. A reset will clear the latch and the MODE1 control bit,
thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the ISCR masks all external interrupt
requests. A latched interrupt request is not presented to the interrupt
priority logic unless the corresponding IMASK bit is clear.
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
(See
Freescale Semiconductor, Inc.
•
•
Table 15-1. IRQ I/O Register Summary
For More Information On This Product,
Figure
Vector fetch or software clear
Return of the interrupt pin to logic 1
Read:
Write:
External Interrupt Module (IRQ1)
15-2).
Go to: www.freescale.com
Bit 7
R
R
0
= Reserved
6
R
0
5
R
0
4
R
0
External Interrupt Module (IRQ1)
IRQF
3
R
ACK
Functional Description
2
0
Advance Information
IMASK
1
MODE
Bit 0
201
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