MC68HC908AZ32ACFU MOTOROLA [Motorola, Inc], MC68HC908AZ32ACFU Datasheet - Page 188

• Manufacturer Part Number: MC68HC908AZ32ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Computer Operating Properly (COP)
13.3 Functional Description
Advance Information
188
NOTE:
NOTE:
The COP counter is a free-running 6-bit counter preceded by a 12-bit
prescaler. If not cleared by software, the COP counter overflows and
generates an asynchronous reset after 2
cycles, depending on the state of the COP rate select bit, COPRS, in the
CONFIG-1 register. When COPRS = 0, a 4.9152-MHz crystal gives a
COP timeout period of 53.3 ms. Writing any value to location $FFFF
before an overflow occurs prevents a COP reset by clearing the COP
counter and stages 4–12 of the SIM counter.
Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the
COP bit in the reset status register (RSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ pin is held
at V
Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
Freescale Semiconductor, Inc.
Hi
For More Information On This Product,
. During the break state, V
Computer Operating Properly (COP)
Go to: www.freescale.com
Hi
on the RST pin disables the COP.
13
– 2
4
or 2
68HC908AZ32A — Rev 0.0
18
– 2
4
CGMXCLK
MOTOROLA