HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 123
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HD6417615
Manufacturer Part Number
HD6417615
Description
Hardware Manual
Manufacturer
Hitachi Semiconductor
Datasheet
1.HD6417615.pdf
(873 pages)
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3.1
Operation of the on-chip clock pulse generator, and CS0 area bus width specification, are
controlled by the operating mode pins. A crystal resonator or external clock can be selected as the
clock source.
3.2
3.2.1
A block diagram of the on-chip clock pulse generator circuit is shown in figure 3.1.
CKPREQ/CKM
Note: See section 20.4.4, Clock Pause Function.
Section 3 Oscillator Circuits and Operating Modes
CKPACK*
Overview
On-Chip Clock Pulse Generator and Operating Modes
Clock Pulse Generator
EXTAL
CAP1
CAP2
XTAL
CKIO
MD2
MD1
MD0
Figure 3.1 Block Diagram of Clock Pulse Generator Circuit
Oscillator
On/Off
Clock mode control circuit
PLL circuit 2
1, 2, 4
PLL circuit 1
The relationship between the
internal clock frequencies is:
I
Maximum frequencies are:
I , E
DIVM
DIVE
DIVP
E
1/1
1/2
1/4
1/1
1/2
1/4
1/1
1/2
1/4
60 MHz, P
P .
E
External interface
clock
I
CPU/DSP core
clock
P
Peripheral module
clock
system clock
30 MHz.
105
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