HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 288

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bits 7, 5, and 4—Address Multiplex (AMX2–AMX0)
Bit 7: AMX2
0
1
Bit 7: AMX2
0
1
Notes: 1. Reserved. Do not set when SZ bit in MCR is 0 (16-bit bus width).
Bit 6—Memory Data Size (SZ): For synchronous DRAM and DRAM space, the data bus width of
BCR2 is ignored in favor of the specification of this bit.
Bit 6: SZ
0
1
For DRAM interface
For synchronous DRAM interface
2. See section 7.5.11 for the method of connection to a 64-Mbit DRAM with a 2M
configuration.
Bit 5: AMX1
0
1
0
1
Bit 5: AMX1
0
1
0
1
Description
Word (16 bits)
Longword (32 bits)
Bit 4: AMX0
0
1
0
1
0
1
0
1
Bit 4: AMX0
0
1
0
1
0
1
0
1
Description
8-bit column address DRAM
9-bit column address DRAM
10-bit column address DRAM
11-bit column address DRAM
Reserved (do not set)
Reserved (do not set)
Reserved (do not set)
Reserved (do not set)
Description
16-Mbit DRAM (1M 16 bits), 64-Mbit
DRAM (2M 32 bits)*
16-Mbit DRAM (2M 8 bits)*
16-Mbit DRAM (4M 4 bits)*
4-Mbit DRAM (256k 16 bits)
64-Mbit DRAM (4M
64-Mbit DRAM (8M
Reserved (do not set)
2-Mbit DRAM (128k 16 bits)
16 bits)
8 bits)*
2
1
1
1
(Initial value)
32-bit
271