HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 275

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bit 11—Area 0 Burst ROM Enable (BSTROM)
Bit 11: BSTROM
0
1
Bit 10—Reserved: This bit is always read as 0. The write value should always be 0.
Bits 9 and 8—Long Wait Specification for Areas 2 and 3 (AHLW1, AHLW0): When the basic
memory interface setting is made for CS2 and CS3, from 3 to 14 wait cycles are inserted in CS2 or
CS3 accesses when the bits specifying the respective area waits in the wait control register
(W21/W20 or W31/W30) are set as long waits (i.e., are set to 11) (see table 7.4).
Bits 7 and 6—Long Wait Specification for Area 1 (A1LW1, A1LW0): When the basic memory
interface setting is made for CS1, from 3 to 14 wait cycles are inserted in CS1 accesses when the
bits specifying the wait in the wait control register are set as long wait (i.e., are set to 11) (see table
7.4).
Bits 5 and 4—Long Wait Specification for Area 0 (A0LW1, A0LW0): When the basic memory
interface setting is made for CS0, from 3 to 14 wait cycles are inserted in CS0 accesses when the
bits specifying the wait in the wait control register are set as long wait (i.e., are set to 11) (see table
7.4).
Bit 3—Endian Specification for Area 4 (A4ENDIAN): In big-endian mode, the most significant
byte (MSB) is the lowest byte address, and byte data is aligned in order toward the least significant
byte (LSB). In little-endian mode, the LSB is the lowest byte address, and byte data is aligned in
order toward the MSB. When this bit is set to 1, data in read/write accesses to the CS4 space is
rearranged into little endian order before being transferred. This is used for data exchange with a
little-endian processor or when executing a program written with awareness of little-endian mode.
Bit 3: A4ENDIAN
0
1
258
Description
Area 0 is accessed normally
Area 0 is accessed as burst ROM
Description
Big endian
Little endian
(Initial value)
(Initial value)