HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 603

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

590
Serial Data Reception (Asynchronous Mode)
Figure 14.8 shows a sample flowchart for serial reception.
Use the following procedure for serial data reception after enabling the SCIF for reception.
No
No
and DR bits in SC1SSR, and
Read ER, BRK, FER, PER,
Read RDF flag in SC1SSR
Clear RE bit to 0 in SCSCR
from SCFRDR, and clear
RDF flag to 0 in SC1SSR
ORER bit in SC2SSR
FER
Read receive data
All data received?
Start of reception
End of reception
Initialization
ER
Figure 14.8 Sample Serial Reception Flowchart (1)
ORER = 1?
RDF = 1?
PER
BRK
Yes
No
Yes
DR
Error handling
Yes
1
2
3
4
1. PFC initialization: Set the RxD pin, and
2. Receive error handling and break
3. SCIF status check and receive data
4. Serial reception continuation procedure:
the SCK pin if necessary, with the PFC.
detection: Read ER, BRK, FER, PER,
and DR in SC1SSR, and ORER in
SC2SSR, to check whether a receive
error has occurred.
If a receive error has occurred, read the
ER, BRK, FER, PER, and DR flags in
SC1SSR and the ORER flag in SC2SSR
to identify the error. After performing the
appropriate error handling, ensure that
the ORER, BRK, DR, and ER bits are all
cleared to 0. Reception cannot be
resumed if the ORER bit is set to 1. The
setting of the EI bit in SC2SSR
determines whether reception is
continued or halted when any of
PER3–0 or FER3–0 is set to 1.
In the case of a framing error, a break
can be detected by reading the value of
the RxD pin.
read: Read the serial status 1 register
(SC1SSR) and check that RDF = 1, then
read receive data from the receive FIFO
data register (SCFRDR) and clear the
RDF bit to 0. Transition of the RDF bit
from 0 to 1 can also be identified by
means of an RXI interrupt.
To continue serial reception, read at
least the receive trigger set number of
data bytes from SCFRDR, and write 0 to
the RDF flag after reading 1 from it. The
number of receive data bytes in
SCFRDR can be ascertained by reading
the lower bits of the FIFO data count
register (SCFDR). (The RDF bit is
cleared automatically when the DMAC is
activated by an RXI interrupt and the
SCFRDR value is read.)