HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 263

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

DMA Data Access Cycle Break Condition Settings
Register settings: BARA = H'00314156 / BAMRA = H'00000000 / BBRA = H'0094
Set conditions:
On channel A, a user break interrupt is not generated as an instruction fetch is not performed in
a DMAC cycle.
On channel D, a user break interrupt is generated when the DMAC writes H'7* (*: Don't care)
is written by byte access to address H'00055555.
BBRB = H'0000
BBRC = H'0000
BARD = H'00055555 / BAMRD = H'00000000 / BBRD = H'00A9
BDRD = H'00007878 / BDMRD = H'00000F0F
BRCR = H'00000008
All channels independent
Channel A: Address:
Channel B: Not used
Channel C: Not used
Channel D: Address:
Bus cycle: DMAC, instruction fetch, read (operand not
Data:
Bus cycle: DMAC, data access, write, byte
H'00314156; address mask: H'00000000
included in conditions)
H'00055555; address mask: H'00000000
H'00007878; data mask: H'00000F0F
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