HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 502

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Table 11.9 shows the combinations of request mode, bus mode, and address mode that can be
specified in the external request mode.
Table 11.9 Combinations of Request Mode, Bus Mode, and Address Mode Specifiable in
Request Mode
External
request
Notes: O: Can be set
Bus Mode and Channel Priority: When a given channel (1) is transferring in burst mode and
there is a transfer request to a channel (0) with a higher priority, the transfer of the channel with
higher priority (0) will begin immediately. When channel 0 is also operating in the burst mode, the
channel 1 transfer will continue as soon as the channel 0 transfer has completely finished. When
channel 0 is in cycle-steal mode, channel 1 will begin operating again after channel 0 completes
the transfer of one transfer unit, but the bus will then switch between the two in the order channel
1, channel 0, channel 1, channel 0. Since channel 1 is in burst mode, it will not give the bus to the
CPU. This example is illustrated in Figure 11.12.
Bus
state
(when priority order is ch0 > ch1, ch1 is set to burst mode, and ch0 to cycle-steal mode)
CPU
—: Cannot be set
1. The same for high-level and low-level detection.
2. The same for rising-edge detection and falling-edge detection.
CPU
Level
detection*
Edge
detection*
the External Request Mode
DMAC ch1 DMAC ch1 DMAC ch0
Figure 11.12 Bus Status when Multiple Channels are Operating
DMAC ch1
Burst mode
1
2
Byte
Word
Longword
16-byte unit
Byte
Word
Longword
16-byte unit
ch0
DMAC ch1 DMAC ch1
ch1
Burst
Mode
—
—
—
—
O
O
O
O
Dual Address Mode
bus right transfers
DMAC ch1/ch0
DMAC ch0
ch0
Cycle-Steal
Mode
O
O
O
—
O
O
O
O
DMAC ch1 DMAC ch1 DMAC ch0 DMAC ch1 DMAC ch1
ch1
ch0
Burst
Mode
—
—
—
—
O
O
O
O
Single Address Mode
DMAC ch1
Burst mode
Cycle-Steal
Mode
O
O
O
—
O
O
O
O
CPU
CPU
487