HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 571

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCIF.
Bit 4: RE
0
1
Notes: 1. Clearing the RE bit to 0 does not affect the RDF, DR, FER, PER, ORER, ER, and BRK
Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE bit setting is only valid in asynchronous mode when the MP bit in SCSMR is set to 1.
The MPIE bit setting is invalid in synchronous mode and IrDA mode, and when the MP bit is 0.
Bit 3: MPIE
0
1
Note: * Receive data transfer from SCRSR to SCFRDR, receive error detection, and setting of the
Bit 2—Reserved: This bit is always read as 0. The write value should always be 0.
558
RDF and FER in SC1SSR and ORER flags in SC2SSR, is not performed. When receive
data with MPB = 1 is received, the MPB flag in SC2SSR is set to 1, the MPIE bit is cleared
to 0 automatically, and generation of RXI and ERI (when the RIE bit in SCSCR is set to 1)
and FER and ORER flag setting is enabled.
2. Serial reception is started in this state when a start bit is detected in asynchronous
flags, which retain their states.
mode or serial clock input is detected in synchronous mode.
SCSMR settings must be made to decide the reception format before setting the RE bit
to 1.
Description
Reception disabled*
Reception enabled*
Description
Multiprocessor interrupts disabled (normal reception performed) (Initial value)
[Clearing conditions]
Multiprocessor interrupts enabled*
Receive interrupt (RXI) requests, receive-error interrupt (ERI) requests, and
setting of the RDF and FER in SC1SSR and ORER in SC2SSR are disabled
until data with the multiprocessor bit set to 1 is received.
When the MPIE bit is cleared to 0
When data with MPB = 1 is received
2
1
(Initial value)