HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 45

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HD6417615

Manufacturer Part Number
HD6417615
Description
Hardware Manual
Manufacturer
Hitachi Semiconductor
Datasheet

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1.4
State Transitions: The CPU has five processing states: the reset state, exception handling state,
bus-released state, program execution state, and power-down state. Figure 1.3 shows the state
transitions.
WDTOVF: In a reset, this pin becomes an output pin.
Processing States
Note: * clock pause function
Bus request
From any state when
RES = 0 and NMI = 1
received
Bus-released state
Interrupt or DMA
address error
When used for general input/output, attention must be paid to the polarity of
this pin.
Power-on reset state
Bus request
Bus request
cleared
Sleep mode
Figure 1.3 Processing State Transitions
Bus request
received
(SBY = 0)
cleared
instruction
SLEEP
Bus request
RST = 1,
NMI = 1
cleared
request
Bus
Program execution state
Exception-handling state
Exception
RST = 0, NMI = 0
cleared
RST = 0, NMI = 1
Module standby
MSTP
bit
From any state when
RES = 0 and NMI = 0
MSTP
bit set
End of
exception
handling
RST = 1,
NMI = 0
Standby mode
SLEEP
Manual reset state
instruction
(SBY = 1)
Power-down state
CKPREQ = 1 *
SBY bit set and
CKPREQ = 0 *
Reset states
NMI interrupt
27

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