HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 264

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

6.3.9
1. UBC registers can be read and written to only by the CPU.
2. Note the following concerning sequential break specifications:
3. When changing a register setting, the written value normally becomes effective in three cycles.
4. If a user break interrupt is generated by an instruction fetch condition match, and the condition
5. Note the following when specifying an instruction in a repeat loop that includes a repeat
6. Do not execute a branch instruction immediately after reading a PC trace register (BRFR,
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a. As the CPU has a pipeline structure, the order of instruction fetch cycles and memory
b. If, of the channels included in a sequential condition, the channel bus cycle conditions
In an on-chip memory fetch, two instructions are fetched simultaneously. If the fetch of the
second instruction has been set as a break condition, even if the break condition is changed by
modifying the relevant UBC registers immediately after the fetch of the first instruction, a user
break interrupt will still be generated prior to the second instruction. To fix a timing at which
the setting is definitely changed, the last register value written should be read with a dummy
access. The changed setting will be valid from this point on.
is matched again in the UBC during execution of the exception service routine, exception
handling for that break will be executed when the interrupt request mask value in SR becomes
14 or below. Therefore, when masking addresses and setting an instruction fetch/post-
execution condition to perform step-execution, ensure that an address match does not occur
during execution of the UBC’s exception service routine.
instruction as a break condition.
When an instruction in a repeat loop is specified as a break condition:
a. A break will not occur during execution of a repeat loop comprising no more than three
b. When an execution-times break is set, an instruction fetch from memory will not occur
BRSR, or BRDR).
cycles is determined by the pipeline. Therefore, a break will occur if channel condition
matches in the bus cycle order satisfy the sequential condition.
constituting the first break conditions of adjacent channels are specified as a pre-execution
break (PCB bit cleared to 0 in BRCR) and an instruction fetch (designated by the break bus
cycle register), note that when the bus cycle conditions for the two channels are matched
simultaneously, a break is effected and the BRCR condition match flags are set to 1.
instructions.
during execution of a repeat loop comprising no more than three instructions.
Consequently, the value in the break execution times register (BETRC or BETRD) will not
be decremented.
Usage Notes