HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 333

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

7.5.9
If the CPU and DMAC or E-DMAC are accessed sequentially and the first access is to SDRAM
and also in the auto precharge mode, the auto precharge cycle (Tap) of the first access may overlap
the second access if the second access is to a different memory space or to a different bank of the
same SDRAM. (Even if the second access is to the normal space, there may be an overlap with the
Tap cycle.) For this reason, it appears for the number of cycles of the second access as if access
takes place sooner (by the number of Tap cycles) than it actually does. Specific cases in which an
overlap occurs are listed in table 7.7. Also, figure 7.32 shows is a conceptual diagram of an
overlap that occurs when memory spaces CS2 and CS3 are connected to SDRAM (table 7.7, No.
3).
Table 7.7
No.
1
2
3
4
316
First access
to CS2 space
Figure 7.32 Conceptual Diagram of Overlap (Conditions: SDRAM Connected to CS2 Space
First Access
Space CS3, auto precharge Access to different space among CS0, CS1, CS2, and CS3
mode
Space CS2, auto precharge Access to different space among CS0, CS1, CS2, and CS3
mode
(RAS Precharge Time Set to 2 Cycles) and SDRAM Connected to CS3 Space)
Overlap Between Auto Precharge Cycle (Tap) and Next Access
Cases of Overlap Between Tap Cycle and Next Access
Tr
Tc
Td1
Second Access
Access to different bank in CS3
Access to different bank in CS2
Td2
Td3
Td4
Second
access to
CS3 space
Tde
Overlap
Tap
Tr
Tap
Tc
Td1
Td2