HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 460

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Rx Descriptor 0 (RD0): RD0 indicates the receive frame status. The CPU and E-DMAC use RD0
to report the frame transmission status.
Bit 31—Rx Descriptor Active (RACT): Indicates that this descriptor is active. The E-DMAC
resets this bit after receive data has been transferred to the receive buffer. On completion of
receive frame processing, the CPU sets this bit to prepare for reception.
Bit 31: RACT
0
1
Bit 30—Rx Descriptor List Last (RDLE): Indicates that this descriptor is the last in the receive
descriptor list. After completion of the corresponding buffer transfer, the E-DMAC references the
first receive descriptor. This specification is used to set a ring configuration for the receive
descriptors.
Bit 30: RDLE
0
1
Description
The receive descriptor is invalid
Indicates that the receive buffer is not ready (access disabled by E-DMAC), or
this bit has been reset by a write-back operation on termination of E-DMAC
frame transfer processing (completion or suspension of reception)
If this state is recognized in an E-DMAC descriptor read, the E-DMAC
terminates receive processing and receive operations cannot be continued
Reception can be restarted by setting RACT to 1 and executing receive
initiation.
The receive descriptor is valid
Indicates that the receive buffer is ready (access enabled) and processing for
frame transfer from the FIFO has not been executed, or that frame transfer is in
progress
When this state is recognized in an E-DMAC descriptor read, the E-DMAC
continues with the receive operation
Description
This is not the last receive descriptor list
This is the last receive descriptor list (the next descriptor is inactive)
445