HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 390

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

9.1.3
The EtherC has signal pins compatible with the 18-pin MII specified in the IEEE802.3u standard,
and three related signal pins to simplify connection to the PHY-LSI. The pin configuration are
shown in table 9.1.
Table 9.1
Type
MII
Other
374
Abbre-
viation
TX-CLK
RX-CLK
TX-EN
ETXD0–
ETXD3
TX-ER
RX-DV
ERXD0–
ERXD3
RX-ER
CRS
COL
MDC
MDIO
LNKSTA
EXOUT
WOL
Pin Configuration
MII Pin Functions
Name
Transmit clock
Receive clock
Transmit enable
Transmit data (4-bit) Output
Transmit error
Receive data valid
Receive data (4-bit)
Receive error
Carrier detect
Collision detect
Management data
clock
Management data
input/output
Link status
General-purpose
external output
Wake-On-LAN
I/O
Input
Input
Output
Output
Input
Input
Input
Input
Input
Output
Input/
output
Input
Output
Output
Function
TX-EN, ETXD0 to ETXD3, TX-ER timing
reference signal
RX-DX, ERXD0 to ERXD3, RX-ER timing
reference signal
Indicates that transmit data is ready on
ETXD0 to ETXD3
4-bit transmit data
Notifies PHY-LSI of error during transmission
Indicates that there is valid receive data on
ERXD0 to ERXD3
4-bit receive data
Identifies error state occurring during data
reception
Carrier detection signal
Collision detection signal
Reference clock signal for information
transfer via MDIO
Bidirectional signal for exchange of
management information between STA and
PHY
Inputs link status from PHY-LSI
External output pin
Magic packet reception