HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 256

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

6.3.6
Sequential Break
Channel C to Channel D: When SEQ1 in BRCR is set to 0 and SEQ0 is set to 1, a sequential
break occurs when the conditions are met for channel C and then channel D, in that order. This
causes the BRCR condition match flag for each channel to be set to 1.
If the break conditions for channels C and D are met at the same time, and the conditions had not
already been met for channel C, the conditions are considered to be met for channel C alone, in the
same manner as if the conditions were met for channel C first. Also, if the conditions for channel
C have already been met when the break conditions for channels C and D are met at the same
time, the conditions for channel D are considered to be met and a break occurs.
Channel B to Channel C to Channel D: When SEQ1 in BRCR is set to 1 and SEQ0 is set to 0, a
sequential break occurs when the conditions are met for channel B, channel C, and then channel
D, in that order. This causes the BRCR condition match flag for each channel to be set to 1.
If the break conditions for channels B and C are met at the same time, and the conditions had not
already been met for channel B, the conditions are considered to be met for channel B. Also, if the
conditions for channel B have already been met when the break conditions for channels B and C
are met at the same time, the conditions for channel C are considered to be met.
If the break conditions for channels C and D are met at the same time, and the conditions had not
already been met for channel C, the conditions are considered to be met for channel C. Also, if the
conditions for channel C have already been met when the break conditions for channels C and D
are met at the same time, the conditions for channel D are considered to be met and a break
occurs.
Channel A to Channel B to Channel C to Channel D: When SEQ1 in BRCR is set to 1 and
SEQ0 is set to 1, a sequential break occurs when the conditions are met for channel A, channel B,
channel C, and then channel D, in that order. This causes the BRCR condition match flag for each
channel to be set to 1.
If the break conditions for channels A and B are met at the same time, and the conditions had not
already been met for channel A, the conditions are considered to be met for channel A. Also, if the
conditions for channel A have already been met when the break conditions for channels A and B
are met at the same time, the conditions for channel B are considered to be met.
If the break conditions for channels B and C are met at the same time, and the conditions had not
already been met for channel B, the conditions are considered to be met for channel B. Also, if the
conditions for channel B have already been met when the break conditions for channels B and C
are met at the same time, the conditions for channel C are considered to be met.
If the break conditions for channels C and D are met at the same time, and the conditions had not
already been met for channel C, the conditions are considered to be met for channel C. Also, if the
conditions for channel C have already been met when the break conditions for channels C and D
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