HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 343

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HD6417615

Manufacturer Part Number
HD6417615
Description
Hardware Manual
Manufacturer
Hitachi Semiconductor
Datasheet

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An address comparator is provided to detect matches of row addresses in burst mode. When this
function is used and the BE bit in MCR is set to 1, setting the MCR’s RASD bit (which specifies
RAS down mode) to 1 places the SH7615 in RAS down mode, which leaves the RAS signal
asserted. The access timing in RAS down mode is shown in figures 7.41 and 7.42. When RAS
down mode is used, the refresh cycle must be less than the maximum DRAM RAS assert time
tRAS when the refresh cycle is longer than the tRAS maximum.
326
Note: * DACKn waveform when active-low is specified
Read
Write
CKIO
A24–A16
A15–A1
RAS
CASn
RD/WR
RD
D31–D0
RD/WR
RD
D31–D0
DACKn *
Tp
Figure 7.40 Burst Access Timing
Tr
Tc1
Tc2
Tc1
Tc2

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