HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 576

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bit 3—Framing Error (FER): Indicates a framing error in the data read from the receive FIFO data
register (SCFRDR).
Bit 3: FER
0
1
Bit 2—Parity Error (PER): In asynchronous mode, indicates a parity error in the data read from
the receive FIFO data register (SCFRDR).
Bit 2: PER
0
1
Bit 1—Receive Data Register Full (RDF): Indicates that the received data has been transferred to
the receive FIFO data register (SCFRDR), and the number of receive data bytes in SCFRDR is
equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO
control register (SCFCR).
Description
There is no framing error in the receive data read from SCFRDR (Initial value)
[Clearing conditions]
There is a framing error in the receive data read from SCFRDR
[Setting condition]
When there is a framing error in SCFRDR read data
Description
There is no parity error in the receive data read from SCFRDR
[Clearing conditions]
There is a parity error in the receive data read from SCFRDR
[Setting condition]
When there is a parity error in SCFRDR read data
In a reset or in standby mode
When there is no framing error in SCFRDR read data
In a reset or in standby mode
When there is no parity error in SCFRDR read data
(Initial value)
563