AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 22

• Manufacturer Part Number: AM79C940JC/W
• Manufacturer: AMD [Advanced Micro Devices]

DXCVR Configuration—SLEEP Operation
Note:
1. RWAKE and ASEL are located in the PHY Configuration Control register (REG ADDR 15). PORTSEL [1–0] and ENPLSIO
Note:
1. RWAKE and ASEL are located in the PHY Configuration Control register (REG ADDR 15). PORTSEL [1–0] and ENPLSIO
22
Sleep
SLEEP
Pin
are located in the PLS Configuration Control register (REG ADDR 14). All bits must be programmed prior to the assertion of
the SLEEP pin.
are located in the PLS Configuration Control register (REG ADDR 14).
Pin
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
RWAKE
ASEL
Bit
0
1
1
1
1
1
1
1
1
0
Bit
X
0
0
0
0
1
1
AWAKE
Bit
LNKST
0
0
0
0
0
0
0
1
1
1
HIGH
LOW
Pin
X
X
X
X
X
ASEL
Bit
X
X
0
0
0
0
1
1
1
1
DXCVR Configuration—Normal Operation
PORTSEL
[1-0] Bits
Impedance
Impedance
Impedance
Impedance
Impedance
Impedance
Impedance
XX
0X
00
01
10
0X
11
LNKST
HIGH
LOW
High
High
High
High
High
High
High
Pin
X
Am79C940
PORTSEL
[1–0] Bits
ENPLSIO
XX
0X
0X
0X
0X
0X
00
01
10
11
BIT
X
X
X
X
X
X
X
10BASE-T with EADI port
10BASE-T with EADI port
10BASE-T with EADI port
AUI with EADI port
AUI with EADI port
AUI with EADI port
Description
10BASE-T
Interface
SIA Test Mode
Invalid
Invalid
Description
Sleep
Mode
10BASE-T
10BASE-T
Interface
DAI port
GPSI
AUI
AUI
Impedance
Impedance
Function
Function
HIGH
HIGH
HIGH
LOW
LOW
LOW
High
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
Pin
High
Pin